FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
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YouTubeFPGA Revolution
FPGA 25 - Shared PS-PL AXI BRAM Application on Zynq SoC FPGA (Verilog)
In this episode, we're building a complete Zynq SoC FPGA application demonstrating a shared AXI BRAM architecture where both the programmable logic (PL) and the processing system (PS) share a 2K by 32-bit BRAM memory and able to exchange data through this shared BRAM buffer. To test this design, we would initiate writing 32-bit counter data ...
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